1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory (DRAM) having an improved refresh timing.
2. Description of the Related Art
In the DRAM, the data is stored in a capacitor of a memory cell on the basis of whether or not there is a charge in the capacitor. Accordingly, the data must be refreshed to hold it in the capacitor, since the data will be lost with the lapse of time, due to a leakage of current from the capacitor.
Therefore, the DRAM is set to two modes, i.e., a read/write mode for reading or writing the data, and a refresh mode for refresh the data. In this case, although the operation speed of the DRAM depends on the read/write and the refresh operation speed at those modes, particularly, the timing of the refresh mode becomes an important factor for a high speed operation of the DRAM.
Consequently, the timing of the refresh mode must be improved to achieve a high speed operation of the DRAM.